Here is the thing nobody tells you about a processor. It is flat for a boring reason.
To make a transistor in silicon you have to anneal it. Dopants have to be driven into the lattice and the damage from implantation has to be healed, and that happens somewhere around 1,000 degrees C. Copper interconnect melts at 1,085 degrees C and degrades well below that. So the order of operations is fixed: you make all the transistors first, in one plane, and then you wire them from below upward in cooler steps.
Once the wiring exists, you can never go back up to transistor temperature. The first layer of devices is the last layer of devices.
That single constraint shapes everything above it. It is why logic and memory are separate dies. It is why a training run spends most of its energy on traffic instead of arithmetic. It is why the industry's answer to more compute is more square metres of fab and more gigawatts of grid.
I have been working on this for a year with Dr. Jeremy Barton, who founded the NanoDynamics Institute after fifteen years at CBN Nano Technologies. He builds molecular machines. I am building the company that points them at semiconductors. This post is the argument, including the part that does not work yet.
The node number is marketing
Start with the thing everybody quotes.
A foundry sells you a "2 nanometre" process. Nothing on that chip is 2 nanometres. The name is a commercial label that stopped tracking any physical dimension around the 28 nm generation. What matters underneath are the pitches: contacted gate pitch, metal pitch, fin pitch. Those are the numbers that decide how much you can put in a square millimetre.
Those numbers have slowed down badly. Metal pitch in leading-edge logic sits in the low twenties of nanometres and the smallest half pitch that production lithography actually resolves has moved very little in a decade, while the label on the box fell from 10 to 2. The gains still arriving are real, but they come from architecture: FinFET to gate-all-around, backside power delivery, higher stacks of the same flat layer, denser packaging around the die.
That is not a complaint about the industry. Those are hard, excellent pieces of engineering. It is an observation about where the remaining headroom is. We are optimizing placement inside one plane because we cannot get out of the plane.
And the exit from the plane is blocked by a thermal budget, not by a physics unknown.
The energy is in the trip, not the sum
Now look at where the joules actually go. Horowitz put the canonical table on a slide at ISSCC in 2014, measured at 45 nm. The ratios have moved since, but not the shape.
| Operation | Energy |
|---|---|
| 32-bit integer add | 0.1 pJ |
| 32-bit SRAM read (on chip) | 5 pJ |
| 32-bit read from HBM | ~125 pJ |
| 32-bit read from off-chip DRAM | 640 pJ |
The arithmetic is free. Fetching the operand costs roughly 1,250 times more than adding it, and that is with high bandwidth memory sitting on the same interposer a few millimetres away. Go to ordinary DRAM and the ratio gets worse.
This is the real cost structure of modern AI. A transformer is mostly a memory scheduling problem wearing a mathematics costume. Every architectural trick of the last five years, from tiling to flash attention to KV cache compression, is fundamentally an attempt to pay that transport bill fewer times.
So the useful question is not how to make a cheaper transistor. It is how to delete the trip.
Die stacking already attacks this, and it works. HBM exists, hybrid bonding exists, chiplets exist. But bonding joins finished dies at a pitch measured in microns. It brings memory closer. It does not put a logic device directly on top of the memory cell it reads.
To do that you need to build a device at a temperature the layer below survives. Which brings us back to the wall.
Room temperature placement
There is a second way to make a structure. Instead of growing a film and cutting away everything you do not want, you put each piece where it belongs.
Biology does this constantly at ambient temperature. A ribosome positions amino acids to angstrom accuracy in water at 37 degrees C, driven by chemistry rather than heat. That machine is proof of concept for the whole category: precise construction with no thermal budget at all.
Barton's platform is a designed version of the same idea. Proteins, designed computationally and expressed biologically, act as actuated arms mounted on a DNA scaffold. The scaffold holds the geometry. The arms move and place material. Underneath sits a MEMS and CMOS stage built in a normal fab, which addresses the arms electrically and reads back what they did.
Three properties matter for chips.
It runs cold. There is no anneal. Whatever is under the placement layer stays intact, so devices can be built on top of finished wiring rather than beneath it.
It is parallel by area. A scanning tunnelling microscope also moves atoms, beautifully, and the field just demonstrated atomically precise mechanosynthesis on hydrogenated silicon at yields between 84 and 97 percent. But an STM is one tip doing one thing at a time, usually at 4 K. An array of arms scales the way a display scales: you add area, not time.
The material it places is better than silicon. Carbon nanotube field effect transistors are the obvious payload. Device-level work puts them roughly an order of magnitude ahead of silicon on energy-delay product, and Stanford's N3XT programme argues that monolithic CNT logic sitting directly on resistive memory could reach three orders of magnitude at the system level, precisely because the transport bill above collapses.
None of this is my idea. The literature is public and it is the reason I believe the thesis at all.
What is already proven, by other people
Five results, five different architectures. This is the honest ladder.
| Result | Who | What it showed |
|---|---|---|
| DNA origami positioned carbon nanotubes to about 6 nm, one junction worked as an FET | Caltech, Nature Nanotechnology 2010 | Static templating in solution, not an actuated arm |
| A 25 nm DNA arm positioned to 2.5 nm at 25 Hz under piconewton forces | TU Munich, Science 2018 | Electrically driven nanomechanical actuation is real |
| RV16X-NANO, a 16-bit RISC-V processor from 14,000 carbon nanotube FETs | MIT, Nature 2019 | CNT logic can be manufactured at circuit scale |
| A carbon nanotube tensor processing unit, 3,000 CNFETs | Peking University, Nature Electronics 2024 | CNT compute is competitive on the workload that matters |
| N3XT monolithic 3D, CNT logic on RRAM | Stanford | The system-level prize for removing the memory trip |
Each piece exists. Nobody has put them in one machine.
The part that does not work
Here is where I have to be careful, because this is a company I am raising money for, and the failure mode of founder writing is to skip this section.
Nobody has built the whole machine. Every piece in the table above was demonstrated by a different group, in a different architecture, for a different purpose. Integration is not a formality. Most of the hard engineering left is in making a laboratory result survive the conditions a semiconductor line actually runs under, and that work is not finished.
Thermal noise does not get corrected away. Drift can be calibrated out. Brownian motion of a soft structure at room temperature cannot. It only gets engineered down through stiffer spaceframes and better joints. I do not have a defensible error budget yet, and neither does Barton. Anyone who quotes you a sub-nanometre placement error for a system like this today is guessing.
Throughput is a band, not a number. One arm motion does not equal one placed device. Assembly takes many motions per device. On the other side, the 25 Hz from the Science paper is very conservative; the ceiling for soft DNA structures is closer to 100 kHz, and stiffened structures should run faster. The product of those two uncertainties is wide enough that I present it as a model and refuse to present it as a forecast.
We do not escape the fab. This is the claim I see people reach for and it is wrong. A placed layer still sits on a lithographic wafer. Through the first two phases we still need a foundry for the substrate, the MEMS stage, power delivery, contacts, doping, packaging and test. Our step needs no EUV. The chip around our step still does.
Where this sits in the stack
Given all that, the sane path is additive first.
Phase one and two are a layer that goes on top of a finished foundry wafer. The foundry keeps its customer and its process, and gains a capability it cannot get from lithography, which is device-level placement on top of live interconnect. Nobody has to bet their fab on us to buy the first thing we sell.
Phase three is the assembler cell, where the machine takes over more of the stack each year until the fab supplies a blank substrate and not much else. That is a decade out and it is not what the first money buys.
The first money buys one narrow result: a single arm placing a device on a CMOS stage. No tiling. No placed circuit. The array and the chip come after, because bundling an unproven step with a manufacturing milestone is how these companies quietly die.
Why this is worth doing now
The forcing function is electricity.
World electricity generation runs at roughly 4 terawatts of average power. The stated ambition in this industry is on the order of a terawatt of chip production capacity per year, and the compute build-out already assumes data centre demand that outruns what grids can add. I have written before about why adding that supply is harder than people think, because two thirds of the world's electricity still comes out of a steam turbine and thermodynamics does not negotiate.
You cannot double the grid by 2030. You can change how much compute a gigawatt buys.
The largest single lever there is not a better transistor. It is deleting the 1,250x tax on moving a number from where it is stored to where it is used. That requires building logic on memory rather than beside it, and building on memory requires making devices without cooking the layer underneath.
Which is the wall we started with.
The far end, briefly
Everything above is engineering with a known shape. The rest is worth naming without pretending it is scheduled.
If placement becomes a general manufacturing primitive rather than a semiconductor process, the interesting consequence is not the chip. It is that the most complex component in any machine, the electronics, stops requiring a twenty billion dollar supply chain and starts requiring feedstock, energy and a design file. That changes what a remote industrial site can build for itself, on this planet or off it. It also dissolves a monopoly structure that currently runs through a handful of buildings in Taiwan and the Netherlands.
I am aware of how that sentence reads. It is why the company is organized around one narrow, falsifiable near-term result instead of the vision, and why the vision lives in a blog post rather than on a milestone chart.
What I actually believe
The physics is settled. Molecular machines position matter precisely at room temperature; biology has run the experiment for four billion years and the synthetic versions now exist in the literature. Carbon nanotubes make better transistors than silicon. Putting logic on memory removes most of the energy cost of computing.
What is unsettled is engineering: keeping the structure stiff enough that thermal noise does not eat the placement budget, holding yield across a large array, and wiring ten thousand arms to a control plane that a foundry can actually produce.
That is a much better problem to have than a physics unknown. It is also not a small one, and I would rather write that down publicly now than discover later that I had quietly rounded it off.
Silicon stopped scaling in the dimension that mattered and the industry responded by getting extraordinarily good at rearranging one plane. The plane is the problem. Going up needs a process that does not require a thousand degrees, and the only candidates for that are machines built out of the same stuff we are.